T. Akioka, S. Yukutake, K. Fukui, K. Mitsumoto, A. Hiraishi, K. Nakagawa, N. Akiyama, M. Iwamura, Y. Kobayashi, S. Ikeda, H. Uchida
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Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v
We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.
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