一种高性能低功耗DSP的混合分层时序闭合方法

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI:10.1145/775832.776046

K. Shi, Graig Godwin

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引用次数: 2

摘要

本文提出了一种混合分层时序闭合方法，结合了基于子芯片的分层时序闭合方法和基于平面设计的逻辑-物理组合优化方法的优点，用于150万门高性能超低功耗DSP，该方法已在许多无线应用中得到应用。给出了该方法的原理和实现细节。

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Hybrid hierarchical timing closure methodology for a high performance and low power DSP

A hybrid hierarchical timing closure methodology has been developed to combine strength of the subchip based hierarchical timing closure method and flat design based logic-physical combined optimization method for a 1.5 million gates, high performance and ultra-low power DSP which has been used in a number of wireless applications. The principle and the implementation details of the methodology are provided.

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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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