{"title":"一个6Gbps串行链路发射机与预强调","authors":"Chih-Hsien Lin, Chung-Hong Wang, S. Jou","doi":"10.1145/1119772.1119948","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"300 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A 6Gbps Serial Link Transmitter with Pre-emphasis\",\"authors\":\"Chih-Hsien Lin, Chung-Hong Wang, S. Jou\",\"doi\":\"10.1145/1119772.1119948\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"300 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-01-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1119772.1119948\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1119772.1119948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
摘要
在本文中,我们提出了一种新的6Gbps SATA发射机。发射机由PISO,驱动器,预强调和锁相环构成,用于1-5米电缆。设计了一个带锁相环和片内终端的发射机测试芯片,验证了设计方法。整个电路采用TSMC 0.18 mum 1P6M 1.8 V CMOS工艺实现。整个测量的发射机抖动约为44ps, 6Gbps情况下的功耗为68mw。
In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case.