采用0.35μm CMOS技术集成100V LDMOS器件

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI:10.1109/ISPSD.2011.5890819

S. T. Kong, P. Stribley, Chris Lee, M. Ong

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引用次数: 4

摘要

本文介绍了用0.35μm CMOS技术成功集成100V LDMOS器件的方法。这些集成器件是增强型n型和p型LDMOS，可与薄(14nm)和厚(40nm)栅极氧化物层兼容。击穿电压大于100V, RDS (ON) =200/180mΩ。n型LDMOS的mm2和RDS (ON) =690/640mΩ。14nm/40nm栅氧化层厚度的p型LDMOS为mm2。

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Integration of 100V LDMOS devices in 0.35μm CMOS technology

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm² for N-type LDMOS and RDS (ON) =690/640mΩ.mm² for P-type LDMOS with 14nm/40nm gate oxide thickness.

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2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs

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