{"title":"一种2gbit /s Si双极性交点开关lsi电路设计","authors":"M. Suzuki, N. Yamanaka, M. Hirata, S. Kikuchi","doi":"10.1109/VLSIC.1989.1037491","DOIUrl":null,"url":null,"abstract":"A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs\",\"authors\":\"M. Suzuki, N. Yamanaka, M. Hirata, S. Kikuchi\",\"doi\":\"10.1109/VLSIC.1989.1037491\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.\",\"PeriodicalId\":136228,\"journal\":{\"name\":\"Symposium 1989 on VLSI Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1989 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1989.1037491\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs
A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.
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