Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA

This paper presents a Configurable Systolic-based Pyramidal Neuron (CSPN) unit that can be used to accelerate the different Deep Neural Network (DNN) algorithms. The proposed CSPN unit is suggested to be one of the new embedded blocks that could replace the conventionally embedded blocks, such as the DSP blocks, in the silicon fabric architectures of the Field Programmable Gate Array (FPGA) chips in order to enhance their computational performance for accelerating the different DNN-based systems. The design of the proposed CSPN unit is fully optimized for Deep Learning (DL) algorithms, especially for the Convolutional Neural Networks (CNN) using VHSIC Hardware Description Language (VHDL). The proposed CSPN unit consists of four main stages: the Systolic-based Multiplier Array Grid, Parallel Signed Adder unit, RELU Activation Function Unit, and the Fixed-Point Configuration Unit. Each single CSPN unit can achieve a computational throughput up to 6.22 Giga Operation per Second (GOPS) using the high-density Stratix V FPGAs for a 3×3 kernel filter input case.