赛灵思FPGA设计的快速模块化组装

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI:10.1109/FPL.2013.6645620

A. Love, P. Athanas

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引用次数: 3

摘要

本文提出了一种可选的FPGA设计编译流程，减少了实现设计所需的后端时间。从油腻前端开始，到TFlow后端，该流程包括一个快速的设计组装方法，与供应商工具解耦。这使得类似软件的周转时间能够更快地进行原型设计并提高生产率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Rapid modular assembly of Xilinx FPGA designs

This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow consists of a rapid method for design assembly, decoupled from the vendor tools. This enables software-like turnaround time for faster prototyping and increased productivity.

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2013 23rd International Conference on Field programmable Logic and Applications

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