M. Carmona, Q. Hubert, L. Lopez, F. Julien, J. Ogier, D. Goguenheim, L. Beauvisage
{"title":"有源区域栅极接触的研究","authors":"M. Carmona, Q. Hubert, L. Lopez, F. Julien, J. Ogier, D. Goguenheim, L. Beauvisage","doi":"10.1109/SBMICRO.2014.6940082","DOIUrl":null,"url":null,"abstract":"In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":" 38","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Study of gate contact over active area\",\"authors\":\"M. Carmona, Q. Hubert, L. Lopez, F. Julien, J. Ogier, D. Goguenheim, L. Beauvisage\",\"doi\":\"10.1109/SBMICRO.2014.6940082\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.\",\"PeriodicalId\":244987,\"journal\":{\"name\":\"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"volume\":\" 38\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBMICRO.2014.6940082\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMICRO.2014.6940082","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.