M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu
{"title":"85ghz完全集成的全数字分数频率合成器,用于55纳米BiCMOS的e波段回程和雷达应用","authors":"M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu","doi":"10.1109/ESSCIRC.2016.7598321","DOIUrl":null,"url":null,"abstract":"This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"25 20","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS\",\"authors\":\"M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu\",\"doi\":\"10.1109/ESSCIRC.2016.7598321\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"25 20\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598321\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598321","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS
This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.