85ghz完全集成的全数字分数频率合成器,用于55纳米BiCMOS的e波段回程和雷达应用

M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu
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引用次数: 3

摘要

本文提出了一种基于低噪声42.5 ghz SiGe四核VCO锁定在标准40 mhz晶体单元上的完全集成和无杂散分数频率合成器。因此,在窄带宽下获得最佳信噪比。参考杂散低于-80 dBc,这要归功于0.5 kHz至50 kHz范围内的可编程数字环路滤波器。锁相环结构对波束形成的相位偏移进行数字控制,并对压控振荡器进行线性化,以确保恒定的截止频率和最佳的信噪比。与需要校准的两点调制相反,雷达调制只需在环路滤波器之后和VCO线性化器之前的一点添加。这些模块——XO、锁相环和倍频器——被封装在BGA基板中。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS
This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.
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