{"title":"相位-幅值噪声转换的正交LC-VCO相位降噪技术","authors":"Chih-Wei Yao, A. Willson","doi":"10.1109/ISSCC.2006.1696109","DOIUrl":null,"url":null,"abstract":"A phase-noise reduction technique for quadrature VCOs reduces and shapes the transistor thermal noise injected into the system, and also provides a phase-to-amplitude noise conversion mechanism to further reduce phase noise. Two experimental designs provide 17% and 1% tuning ranges centered at 5.1GHz and 5.3GHz with phase noise of -132.6dBc/Hz and -134.4dBc/Hz at a 1MHz offset, respectively","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"42","resultStr":"{\"title\":\"A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion\",\"authors\":\"Chih-Wei Yao, A. Willson\",\"doi\":\"10.1109/ISSCC.2006.1696109\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A phase-noise reduction technique for quadrature VCOs reduces and shapes the transistor thermal noise injected into the system, and also provides a phase-to-amplitude noise conversion mechanism to further reduce phase noise. Two experimental designs provide 17% and 1% tuning ranges centered at 5.1GHz and 5.3GHz with phase noise of -132.6dBc/Hz and -134.4dBc/Hz at a 1MHz offset, respectively\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"42\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696109\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696109","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion
A phase-noise reduction technique for quadrature VCOs reduces and shapes the transistor thermal noise injected into the system, and also provides a phase-to-amplitude noise conversion mechanism to further reduce phase noise. Two experimental designs provide 17% and 1% tuning ranges centered at 5.1GHz and 5.3GHz with phase noise of -132.6dBc/Hz and -134.4dBc/Hz at a 1MHz offset, respectively