Characterization of Optical End-Point Detection for Via Reveal Processing

Abstract

In the general context of scaling, the 3D stacked system architecture is considered today, more than ever, as one of the future alternatives. Multiple options are still under investigation, but common process modules can already be identified. An important element of 3D integration is the backside Through-Silicon Via (TSV) reveal process after wafer bonding and thinning, also called Via Reveal. This has gained more and more interest in recent years as process robustness and stability will impact the device electrical performances and reliability. Moreover, subsequent processing such as bumping or RDL (Redistribution Layers) processing directly rely on successfully exposed TSVs. Different approaches have been developed for via reveal and have already been adopted by industry. So far, different studies have been carried out investigating issues affecting process integration, mainly to assess non-uniformity issues. Indeed, multiple factors can lead to variability within the process that will affect the TSV reveal performances. The consequences are large within-wafer variations, wafer-to-wafer non-uniformities and lot-to-lot variations. The robustness and stability of the via reveal process can be drastically improved by using an in-situ optical endpoint detection (EPD) system. The focus of this paper is to introduce an innovative approach where the via reveal process is controlled by an integrated optical EPD system during the reactive Si dry etch to expose the backside TSVs. The first part of the study introduces the impact of mask open area (or TSV density) on the EPD traces. As the system is based on optical reflection, the reflected signal intensity can vary according to the revealed TSVs. The second part focuses on the study of the optical EPD window modulation where the wafer area of interest can be extended within the wafer (center and along the wafer). This approach can be beneficial where the incoming Si thickness after grind and the TSV depth profile have variability wafer to wafer. A comparison of low TSV density and high TSV density is also shown. Finally, directions for process improvement are discussed.