Novel design of fast and compact SHA-1 algorithm for security applications

Abstract

In this work, a novel architecture of Secure Hash Algorithm-1(SHA-1) for increased throughput and reduced area is presented. Various acceleration techniques are applied such as pre-computation, loop unfolding, and pipelining simultaneously. Carry Save Adder using Carry Lookahead Adder in its final stage is used for multi-input addition function to achieve high performance. The proposed architecture is designed using VHDL language. The synthesis and simulation work is performed in Xilinx ISE Design Suite 13.2 tool. The present implementation of SHA-1 offers better results as compared to previous works.