Synthesis of robust controllers for GALS_FPGA from multi-burst graph specification

Abstract

Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used to implement circuits in FPGAs (Field Programmable Gate Array). Although these devices have the benefits of low-cost and short development time, there's a major drawback which is implementing Asynchronous Interfaces (AI) in FPGA devices. There's a typical AI design style which is based on asynchronous controllers that provides communication between modules (called ports), but Port controllers are subject to essential-hazard when implemented FPGAs. This paper proposes a method based on direct mapping to implement these ports. It begins with an MBG (multi-burst graph) specification and makes use of the essential signal concept to check if the resulting circuit is hazard-free, or to point potential essential-hazard problems in the circuit. By satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.