Virtex FPGA implementation of a polyphase filter for sample rate conversion

Abstract

Many practical applications of DSP require the sampling rate of a signal to be changed. This is usually achieved using linear, time-variant finite impulse response (FIR) filters such as polyphase filters. This paper describes the modelling, design and implementation of a polyphase filter using the Xilinx Virtix FPGA technology. Four solutions were explored. The first (obvious) solution involving reducing the number of multipliers by exploiting the proliferation of zeroes in the filter response. In the second and third approaches, the circuit was transformed to reduce the critical path. The fourth approach involved the development of a multiplier that multiplies a fixed number of coefficients.