A high speed low power adder in dynamic logic base on transmission gate

Abstract

Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET transistor gain which in turn depends on transistor size. The power consumption in MOSFET is depends on the switching frequency, sub threshold leakage and switching time. In this paper, author proposed the speed and area efficient transistor base adder using static CMOS pass transistor logic, and shortened the longest critical path to decrease the total critical path delay. The design simulation on microwind layout tool calculates the worst-case delay in nanosecond and total power consumption in microwatt range.