K. Guarini, Paul M. Solomon, Yuan Zhang, Kevin K. Chan, E. C. Jones, Guy M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, Cyril Cabral, Christian Lavoie, Victor Ku, Diane C. Boyd, K. Petrarca, I. V. Babich, J. Treichler, P. Kozlowski, J. Newbury, C. D'Emic, R. M. Sicina, Hon-Sum Philip Wong
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引用次数: 68
Abstract
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
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