Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder

IF 1.7 Q3 COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE
R. Upadhyay, R. Chauhan, Manish Kumar
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引用次数: 0

Abstract

The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed full adders, using metrics such as power dissipation, propagation delay and power delay product. Comparative performance shows that the proposed 1-bit full adder shows average improvement in terms of power dissipation (31.62 nW and 20.84 nW) and average delay (5.07ns and 11.41ns) over the existing 1-bit hybrid and cell 3 full adder circuit.
高效低功耗1位混合全加法器的性能评价
为了实现人机交互,嵌入式系统对低功耗芯片系统的需求大大增加。这种嵌入式系统的主要约束是减少功耗和提高设备的电池性能。本文提出了一种节能、低功耗的混合1位全加法器电路,该电路可以集成在芯片上,以提高嵌入式系统的整体性能。采用Mentor Graphics EDA工具对130纳米工艺设计的1位混合全加法器电路进行了仿真。此外,还使用功耗、传播延迟和功率延迟积等指标与先前提出的全加法器进行了比较。对比性能表明,与现有的1位混合和单元3全加法器电路相比,所提出的1位全加法器在功耗(31.62 nW和20.84 nW)和平均延迟(5.07ns和11.41ns)方面有平均改善。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
1.40
自引率
0.00%
发文量
22
审稿时长
4 weeks
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