A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation

Abstract

Presents a 0.25/spl mu/m CMOS based smart power platform on a P++ substrate with a deep trench high-voltage isolation as a low-cost alternative to SOI in realizing significant analog shrink, reduction of substrate parasitics and 70V high-side capability without affecting analog matching and process complexity.