Thermomechanical Properties of Fan-Out Wafer Level Package with Various Chip and Mold Thickness

Abstract

The 3D package technology has been developed higher performance, higher functionality, smaller and thinner devices for mobile, wearable and IoTs in recent years. Among advanced packaging technologies, advantages of fan-out wafer level package (FOWLP) are its higher I/O density, higher electrical performance, ultra-thin and low power consumption. However, the FOWLP has some mechanical issues about the warpage caused by different coefficient of thermal expansion(CTE) between the various packaging material constituents. We investigated the warpage behavior of FOWLP component with various chip and EMC thickness. The FOWLP component was fabricated by the mold-first process. The 8 × 8 mm2 Si chips (chip thickness: 50, 75 and 100 ?m) were taken placed on the carrier wafer. After that, compression mold (EMC mold thickness: 300 and 460 ?m) was used to fabricate the molded wafer. Redistribution layer (RDL) was fabricated on the molded chip by photolithography. The warpage behavior of the FOWLP component was analyzed from room temperature to 260 °C using shadow moiré method. The environmental reliability of FOWLP component were evaluated by temperature-humidity bias test and thermal shock test. The warpage property depended on ratio of Si chip to EMC thickness. The warpage of FOWLP component with 300 ?m EMC mold and 100 ?m chip thickness whose ratio of Si chip to EMC thickness is 0.33 is about 100 ?m. However, the warpage of other FOWLP component, ratio of Si chip to mold thickness is less than 0.25, is more than 200 ?m. Electrical resistance of FOWLP component were 1.9~2.6 m? and 1.6~2.2 m? after temperature-humidity bias test and thermal shock test, respectively. The electrical resistance of FOWLP component at all sample increased by more than 1.2 times after temperature-humidity bias test and thermal shock test. Warpage was affected by the ratio of chip to EMC thickness.