An Iterative Scheme for Hierarchical Production Planning in Semiconductor Wafer Fabrication

Abstract

This paper considers a production planning and scheduling problem in a multi-product semiconductor wafer fabrication facility, which copes with the challenging factors including multiple re-entrant loops and diverse equipment characteristics. This work proposes a hierarchical production planning and scheduling approach that uses an iterative method for refining production plans to solve this problem. A production plan serving multiple objectives is derived by solving a linear programming problem, which is followed by a simulation run with a given scheduling rule to evaluate the performance gap. The planning and the simulation phases are executed in an iterative manner to reduce the performance gap between the planned production level and that from simulation outcome. A scheduling rule is proposed whereby the priority of a wafer is derived from the state of work-in-process (WIP) or production at that instant. The performance of the proposed method is assessed based on numerical simulations carried on Intel mini fab taking due date based demands for multiple products into consideration.