Devise and establishment of property specification language to verify the complex behaviour of FPGA Ethernet IP core

Abstract

FPGA Ethernet IP cores are widely used in the all Aerospace and defense communication systems. If the IP core fails to function as designed then whole communication process may fail. So it is important to verify this complex FPGA Ethernet IP core effectively. This paper aims in development of real-time verification environment for the FPGA Ethernet IP core using Formal Methods based approach. Under formal methods the Assertion-based verification (ABV) is one of the effective techniques for verification of IP cores and its interfaces. PSL (Property Specification Language) is an assertion language where it is used to verify the systems developed using Hardware Descriptive Language (HDL). PSL captures the requirement specifications and verify the functional and behavioral properties of Ethernet IP core in the early phase of the systems engineering lifecycle. The Xilinx 10G Ethernet Mac IP core is used to demonstrate the effectiveness of the PSL for functional verification of the IP core.