Sagnik Mukhopadhyay, Pritha Banerjee, S. Sur-Kolay
{"title":"Balanced bipartitioning of a multi-weighted hypergraph for heterogeneous FPGAS","authors":"Sagnik Mukhopadhyay, Pritha Banerjee, S. Sur-Kolay","doi":"10.1109/SPL.2011.5782631","DOIUrl":null,"url":null,"abstract":"In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"19 1","pages":"91-96"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.