A verification method for systolic arrays using induction-based theorem provers

Kazuko Takahashi , Hiroshi Fujita
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Abstract

We proprose a method for verifying hardware design with an induction-based theorem prover such as the Boyer–Moore Theorem Prover. As a case study, we apply the method to verification of the correctness of systolic array designs. In verifying circuits, we prove that an implementation satisfies a specification, in particular their functional equivalence. In proving the equivalence, induction is applied to the variables that denote time and position in the circuit. We discuss what lemmas should be used for appropriate application of induction. The lemmas we have found reflect the characteristics of the structure of the circuit. With these lemmas, the method provides a systematic way of verification for systolic arrays and eases the user's burden with respect to the hardware verification.

用基于归纳的定理证明器验证收缩阵列的方法
我们提出了一种用基于归纳的定理证明器(如Boyer-Moore定理证明器)来验证硬件设计的方法。作为一个案例研究,我们应用该方法来验证收缩阵列设计的正确性。在验证电路时,我们证明了一个实现满足规范,特别是它们的功能等价。在证明等效性时,将感应应用于表示电路中时间和位置的变量。我们讨论了适当应用归纳应该使用哪些引理。我们找到的引理反映了电路结构的特点。利用这些引理,该方法为收缩阵列提供了一种系统的验证方法,减轻了用户在硬件验证方面的负担。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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