A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons

Abstract

In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13¿m CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.