A Pragmatic Approach to On-Line Testing

Abstract

Modeling and simulation of time domain faults in digital systems p. 5 Sizing CMOS circuits for increased transient error tolerance p. 11 Low-area on-chip circuit for jitter measurement in a phase-locked loop p. 17 Necessary and sufficient conditions for the existence of totally self-checking circuits p. 25 Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits p. 31 A hierarchical self test scheme for SoCs p. 37 Single-output embedded checkers for systematic unordered codes p. 45 A new dynamic circuit design technique for high performance TSC checker implementations p. 52 New high speed CMOS self-checking voter p. 58 Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks p. 67 Low cost on-line testing of RF circuits p. 73 Hybrid soft error detection by means of infrastructure IP cores p. 79 A comparative study of the design of synchronous and asynchronous self-checking RISC processors p. 89 Testing of hard faults in simultaneous multihreaded processors p. 95 Fault detection enhancement in cache memories using a high performance placement algorithm p. 101 Transient fault emulation of hardened circuits in FPGA platforms p. 109 On the evaluation of SEU sensitiveness in SRAM-based FPGAs p. 115 Asynchronous circuits sensitivity to fault injection p. 121 Designing a high speed decoder for cyclic codes p. 129 Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems p. 135 A signed digit adder with error correction and graceful degradation capabilities p. 141 A novel fault tolerant cache to improve yield in nanometer technologies p. 149 Scrubbing away transients and jiggling around the permanent : long survival of FPGA systems through evolutionary self-repair p. 155 Hardware reconfiguration scheme for high availability systems p. 161 Operating system function reuse to achieve low-cost fault tolerance p. 167 A new code with reduced EMI and partial EC possibilities p. 175 A Matlab based on-chip signal generation and analysis environment for mixed signal circuits p. 176 Automated logic SER analysis and on-line SER reduction p. 177 On the design of long-life reliable systems for ground-based applications p. 178 On-line monitoring capabilities of oscillation test techniques : results demonstration in an OTA p. 179 An intrinsically robust technique for fault tolerance under multiple upsets p. 180 Survey of the algorithms in the column-matching BIST method p. 181 A technique to reduce power and test application time in BIST p. 182