Modeling for critical design and performance of wafer level chip scale package

Y. Liu, Qiuxiao Qian, M. Ring, Jihwan Kim, D. Kinzer
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引用次数: 11

Abstract

Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.
晶圆级晶片级封装的关键设计与性能建模
为了提高晶圆级芯片规模封装(WLCSP)关键设计的性能,进行了全面的有限元分析(FEA)建模。首先,研究了一种非覆盖UBM区域的一层再分布布局(RDL)带蚀刻口袋的铜和一层聚酰亚胺结构(1Cu1Pi设计)的设计。通过有限元建模研究了不同的聚酰亚胺布局、铜厚度、口袋参数和未覆盖的UBM直径。然后,研究了一种叠层金属设计,将溅射铜UBM堆叠在RDL铜层上,并在它们之间放置一层聚酰亚胺(2Cu1Pi)用于WLCSP。通过仿真研究了相同焊料体积下不同焊管直径和相同焊点高度下不同焊管直径的参数。最后对模型与试验的破坏机理进行了相关性和对比分析。
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