An All-Wet, Low Cost RDL Fabrication Process with Electroless Plated Seed/Barrier Layers

Abstract

2.5D/3D IC packaging and fan-out wafer-level packaging (FOWLP) have attracted much attention both from the academics and industries. In these technologies, the manufacturing of redistribution/rerouting layer (RDL) plays an important role. In this paper, an all-wet, low cost RDL fabrication process is designed and experimentally demonstrated, employing photosensitive polyimide (PSPI) as the dielectric layer and electroless plating for the seed/barrier layers. Using the spin coating technique, the PSPI dielectric layer with uniform thickness is formed on the surface of the substrate, followed by the patterning of mirco-vias and the thermal curing. With the help of O2 plasma cleaning for 10 mins, the residual PSPI at the corners of patterned micro-vias is removed completely and the profiles of the patterned micro-vias are further improved. In addition, the rough surface morphology of PSPI layer after the O2 plasma cleaning is beneficial to enhance the adhesion property of the electroless plated seed/barrier layers, which is verified by the standard cross cut test. Finally, with semi-additive process (SAP), fine-profile RDL with micro-vias is successfully fabricated and presented.