Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology

Abstract

This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.