Unconventional transistor sizing for reducing power alleviates threshold voltage variations

Abstract

Digital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (σVTH). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L >; Lmin, W/L <; 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also σVTH. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over Lmin, and examine how such sizing affects delay, power, and power-delay-product of these two gates.