Channel length and width effects on NMOS transistor degradation under constant positive gate-voltage stressing

Abstract

It is pointed out that a reliable gate oxide is the most important component for MOS devices operating under a high gate voltage. Trapped charges and interface states are generated in the oxide under a high gate-voltage bias due to Fowler-Nordheim tunneling. The gate current, charge pumping current, and threshold voltage shift critically depend on the electric field across gate oxide. It is demonstrated that device degradation is a strong function of channel width to channel length ratio (W/L). Under the same stress condition, a higher W/L ratio leads to more severe degradation. This geometric effect is the result of nonuniform distribution of trapped charges and interface states. The densities of trapped charges and the interface states are highest near the source and drain regions and lowest along the isolation edges.<>