Two-stage model for lifetime prediction of highly stable amorphous-silicon thin-film transistors under low-gate field

Abstract

Highly stable a-Si TFTs reported recently with extremely long operating lifetimes under DC gate bias are attractive for analog drivers of the OLEDs in AMOLED displays. At room temperature, the time for the DC saturation current to drop to 50% is predicted to be 100 to 1,000 years. However, the lifetimes were extrapolated with a stretched-exponential model for defect creation in a-Si, based on only month-long room temperature tests. In this study, we present a two-stage threshold voltage shift model for lifetime prediction from temperature dependent measurements. We find that (i) a “unified stretched exponential fit” models the drain current degradation from 60°C to 140°; and (ii) there is a second instability mechanism that initially dominates up to hours or days at low temperatures, so that tests conducted only at room temperature may not predict lifetime accurately.