Power reduction in nanomagnetic logic clocking through high permeability dielectrics

Peng Li, G. Csaba, V. Sankar, X. Sharon Hu, M. Niemier, W. Porod, G. Bernstein
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引用次数: 2

Abstract

Nanomagnetic logic (NML) has emerged as a novel paradigm to realize non-volatile, nanometer scale, ultra-low energy digital logic [1]. Since there are large energy differences between magnetization states, an external stimulus is required for circuit re-evaluation. In our first experiments we applied an off-chip magnetic field along the hard (i.e., short) axis of a group of nanomagnets. Later, structures that generate fields on-chip were demonstrated [2]. These current-carrying copper wires clad with ferromagnetic material (Supermalloy, Ni79Fe16Mo5), can provide local magnetic fields for NML circuits. However, the required current densities could be as high as ∼107 A/cm2 [2]. The ratio of flux density to magnetic field strength (μ = B/H) can be increased by surrounding the magnets with a material of high permeability. While we will need to ensure that the binary state of a magnet is not adversely affected, candidate materials do exist. Freescale demonstrated enhanced permeability dielectrics (EPDs) with embedded magnetic nano-particles to increase the field from a word or bit line in field MRAM without increasing current [3]. That EPD particle sizes are below the superparamagnetic limit helps to ensure that a magnet's state is not unduly influenced. With similar considerations, we have proposed a clocking structure where EPD films surround the nanomagnets, as shown in Fig. 1. With this new design, the magnetic flux can be confined within the EPD film area instead of leaking to the air. As such, the field intensity for switching the nanomagnets can be increased, and the required current density and power for clocking can be reduced (potenitially by μr2 in the case of power). This work shows our efforts of integrating EPD films with nanomagnets for NML clocking.
通过高磁导率电介质降低纳米磁逻辑时钟的功率
纳米磁逻辑(NML)已成为实现非易失性、纳米尺度、超低能量数字逻辑的新范式。由于磁化状态之间存在较大的能量差,需要外部刺激进行电路重估。在我们的第一个实验中,我们沿着一组纳米磁铁的硬(即短)轴施加了一个片外磁场。随后,在芯片上演示了产生场的结构。这些载流铜线包有铁磁材料(Supermalloy, Ni79Fe16Mo5),可以为NML电路提供局部磁场。然而,所需的电流密度可能高达~ 107 A/cm2[2]。用高磁导率材料包裹磁体可以提高磁通密度与磁场强度之比(μ = B/H)。虽然我们需要确保磁体的二元状态不受不利影响,但候选材料确实存在。飞思卡尔展示了嵌入磁性纳米颗粒的增强磁导率介电体(epd),可以在不增加电流的情况下增加磁场MRAM中的字或位线的磁场。EPD颗粒尺寸低于超顺磁极限有助于确保磁铁的状态不受过度影响。基于类似的考虑,我们提出了一种EPD薄膜包围纳米磁铁的时钟结构,如图1所示。通过这种新设计,磁通量可以被限制在EPD膜区域内,而不是泄漏到空气中。这样,开关纳米磁体的场强可以增加,而时钟所需的电流密度和功率可以降低(在功率的情况下可能降低μr2)。这项工作显示了我们将EPD薄膜与纳米磁铁集成在NML时钟中的努力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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