Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

2012 IEEE 62nd Electronic Components and Technology Conference Pub Date : 2012-07-30 DOI:10.1109/ECTC.2012.6248797

C. Ko, Z. Hsiao, Y. J. Chang, P. S. Chen, J. Huang, H. Fu, Y. J. Huang, C. Chiang, C. K. Lee, H. Chang, W. Tsai, Y. -. Chen, W. Lo, K. N. Chen

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引用次数: 6

Abstract

In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.

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基于微凹凸/粘接混合晶圆键合的Cu tsv晶圆级三维集成方案的结构设计、工艺和可靠性

本文提出了一种基于Cu/Sn微凸点和BCB胶杂化键合的晶圆级三维集成方案。为了实现高速数字信号中Cu - TSV和Cu/Sn微接头互连的信号传输效果，通过仿真分析研究了不同TSV节距、微凸点直径和芯片厚度下的插入损耗。开发并集成了TSV制造、微碰撞、混合方案制作、混合键合、晶圆减薄和背面RDL形成等关键技术，实现了三维集成方案。5μm TSV、10μm微凸点、20μm间距、40μm薄晶片和250°C低温W2W杂化键合已成功集成在集成平台上。该方案具有优异的电气性能和可靠性，具有应用于3D产品的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 IEEE 62nd Electronic Components and Technology Conference

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