High quality CVD TaN gate electrode for sub-100 nm MOS devices

Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong
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引用次数: 13

Abstract

In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.
用于亚100nm MOS器件的高品质CVD TaN栅电极
在本文中,我们首次详细评估了CVD TaN作为亚100nm MOS器件潜在栅极材料的物理和电学性能。我们的研究结果表明,使用TBTDET (tertbutylimidoirisdiethylamido tantalum)沉积的CVD TaN薄膜具有优异的热稳定性,其底层超薄SiO/sub /高达1000/spl°/C,并且具有非常稳定的功函数(5eV@800-1000/spl°/C),适合p-MOS器件应用。与PVD TaN相比,采用CVD TaN栅极的MOS器件在p-MOS器件中具有良好的功功能,在高温退火过程中栅极氧化物厚度、漏电流和界面性能具有优异的稳定性,栅极介电介质TDDB可靠性也较好。这些结果表明,CVD TaN可以作为超薄栅极氧化物的栅极电极用于自对准栅优先CMOS工艺。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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