Modular construction of model partitioning processes for parallel logic simulation

Abstract

Logic simulation of a complex processor model in VLSI design is very time consuming. One possibility to increase the simulation speed is to partition the processor model and assign the resulting parts to simulator instances that cooperate over a loosely-coupled system. For corresponding model partitioning processes, we have developed a distributed framework parallelMAP implementing a hierarchical partitioning strategy. It is intended to be used as production environment in VLSI design as well as an experimental test bed for algorithm development. In this paper we describe the possibilities parallelMAP offers for the modular construction of partitioning processes starting from a set of basic sequential and parallel modules. Experimental experiences are given with respect to IBM processor models comprising from 1.5*10/sup 5/ to 2.5*10/sup 6/ elements at gate level.