Jungdal Choi, Seong-Soon Cho, Y. Yim, Jaeduk Lee, H. Kim, Kyung-joong Joo, S. Hur, Heung-Soo Im, Joon Kim, Jeong-Woo Lee, K. Seo, M. Kang, Kyungryun Kim, Jeong-Lim Nam, Kyucharn Park, Moon-Yong Lee
{"title":"Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology","authors":"Jungdal Choi, Seong-Soon Cho, Y. Yim, Jaeduk Lee, H. Kim, Kyung-joong Joo, S. Hur, Heung-Soo Im, Joon Kim, Jeong-Woo Lee, K. Seo, M. Kang, Kyungryun Kim, Jeong-Lim Nam, Kyucharn Park, Moon-Yong Lee","doi":"10.1109/IEDM.2001.979394","DOIUrl":null,"url":null,"abstract":"An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"14 1","pages":"2.1.1-2.1.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.
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