Impact of Q-Time on the Passivation of Al2O3/p-In0.53Ga0.47As Interfaces Using Various Surface Treatments

Abstract

The downscaling of complementary metal-oxide-semiconductor (CMOS)mayneedtheintegrationofIII-Vsemiconductorsandrelated high-k materials, since Si-based devices have reached their physical limitations. Unfortunately, the inherent poor interfacial quality of IIIV substrates and high dielectric constant gate oxides lead to the large defect state densities (Dit) which results in Fermi level pinning and the loss of channel controlling. 1,2 This issue is still a major challenge that needs to be addressed in spite of many achievements in interface passivation treatments. 3‐12 Recently, either ex-situ chemical and in-situ ALD surface treatments of the In0.53Ga0.47As substrates exhibited the strong minority carrier response at inversion region, which means Fermi level can be freely swept through the bandgap of III/V semiconductor. 9‐11 Similarly, O’Connor et al. 12 achieved the strong inversion behavior for n, p-In0.53Ga0.47As substrates with sulfur treatment and ALD-Al2O3 deposition. They also emphasized the impact of the delay time between the ex-situ chemical surface treatment and the ALD chamber loading (Q-time) on the quality of the high-k/III-V interface. The Q-time should be limited as low as possible; otherwise, the interfacial quality of high-k/III-V will be degraded. In this study, p-In0.53Ga0.47As substrates were treated by several chemical solutions with different Q-times prior to ALD chamber loading. Yet the nice C-V response was still observed even after 24 hours of Q-time for the MOSCAP structures studied. In terms of Q-time property, our results have supported the conclusion which might stand in contrast with previous studies, 7,8,12 i.e., reduced transfer time (less than few minutes) is not necessarily a prerequisite for an efficient chemical passivation of Al2O3/In0.53Ga0.47As interfaces. The nature of interface trap states discussed in this work would facilitate further understanding and passivating of high-k/III-V interfaces.