A SystemVerilog approach in system validation with affine arithmetic

Abstract

This paper introduces an original approach to system modeling for performance analysis and optimization. The method presented herein theoretical background is the mathematical field of affine arithmetic chosen for its intrinsic data representation optimal to analysis of the mitigation of variations and refinement of deviations and error analysis. The chosen language of SystemVerilog is beneficial for it is allowing the integration of the validation process and of the verification process for the specific class of mixed signal electrical circuits and systems.