A 4th-order analog continuous-time filter designed using standard cells and automatic digital logic design tools

Abstract

An inverter-transconductor-based continuous-time analog 4th-order low-pass Butterworth filter was described entirely in Verilog hardware description language (HDL) using only standard cells. The physical design was synthesized with automated digital logic place-and-route (APR) CAD tools. APR was achieved in less than a minute making for an enormous improvement compared to traditional manual analog chip layout. A test chip was fabricated in a 0.18um CMOS technology and its performance was experimentally verified. The experimental results document excellent measured performance and a huge physical design timesaving thereby validating the proposed automated design methodology.