Simulation of charge trapping memory with silicon nanocrystals embedded in silicon nitride layer

Abstract

A simulation method for evaluating the performance of CTM with incorporating nanocrystals into the charge trap layer is presented and the effects of bias voltage, charge trap distribution, nanocrystal size, temperature and gate dielectric layer's thickness on program/erase/retention characteristic are studied. It can be a useful tool for designing nanocrystals based CTM.