{"title":"Spin neuron for ultra low power computational hardware","authors":"M. Sharad, G. Panagopoulos, K. Roy","doi":"10.1109/DRC.2012.6257039","DOIUrl":null,"url":null,"abstract":"We propose a device model for neuron based on lateral spin valve (LSV) that constitutes of multiple input magnets, connected to an output magnet, using metal channels. The low-resistance, magneto-metallic neuron can operate at a small terminal voltage of ~20mV, while performing computation upon current-mode inputs. The spin-based neurons can be integrated with CMOS to realize ultra low-power data processing hardware, based on neural networks (NN), for different classes of applications like, cognitive computing, programmable Boolean/non-Boolean logic and analog and digital signal processing [1, 2]. In this work we present analog image acquisition and processing as an example. Results based on device-circuit co-simulation framework show that a spin-CMOS hybrid design, employing the proposed neuron, can achieve ~100x lower energy consumption per computation-frame, as compared to the state of art CMOS designs employing conventional analog circuits [13].","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"9 1","pages":"221-222"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"70th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2012.6257039","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
We propose a device model for neuron based on lateral spin valve (LSV) that constitutes of multiple input magnets, connected to an output magnet, using metal channels. The low-resistance, magneto-metallic neuron can operate at a small terminal voltage of ~20mV, while performing computation upon current-mode inputs. The spin-based neurons can be integrated with CMOS to realize ultra low-power data processing hardware, based on neural networks (NN), for different classes of applications like, cognitive computing, programmable Boolean/non-Boolean logic and analog and digital signal processing [1, 2]. In this work we present analog image acquisition and processing as an example. Results based on device-circuit co-simulation framework show that a spin-CMOS hybrid design, employing the proposed neuron, can achieve ~100x lower energy consumption per computation-frame, as compared to the state of art CMOS designs employing conventional analog circuits [13].