Analytical Model of the Parallel-Connected Silicon Carbide MOSFET Turn-ON Switching Behavior Under Asynchronous Gate Signals

Abstract

Parallel-connected power device is an extensively applied solution in the industry to increase the current rating of the converter system compared with using high-power modules. However, due to the undesired PCB layout or semiconductor fabrication tolerance, mismatched drain-source current (Ids) which speeds up the aging process of a specific device can be introduced. The application of silicon carbide (SiC) devices aggravates this problem due to their higher switching speed. Asynchronous gate signal delay brought by the different driver chip propagation delay, gate loop parasitic inductance, or asynchronous PWM signal is a major reason of transient current imbalance. The analysis of its impact on switching performance is yet to be clarified. In this paper, different types of current imbalance of parallel connected MOSFET are analyzed. An accurate analytical model for deriving the turn-on switching trajectory of parallel-connected SiC MOSFETs under different gate signal delay time is firstly proposed. With the proposed model, the important performance indicators such as turn-on switching energy loss, current stress can be derived with the trajectory model. Experimental study is conducted to validate the proposed model.