How to avoid false lock in SPLL frequency synthesizers

Abstract

In addition to the stable fixed point which should be achieved under steady-state conditions, the Sampling Phase-Locked Loop (SPLL) implemented with a loop fiber has another stable attractor in which an unwanted periodic solution, called false lock, develops in the loop. After the acquisition process, the SPLL either reaches the desired fixed point or gets into false lock, depending on the initial conditions. SPLLs are frequently used in measurement equipment to implement frequency synthesizers and oscillators with high spectral purity and stability. False lock results in a measurement error which has to be avoided. The main goal of this paper is to give a model for the false lock phenomena which explains how the system gets into false lock. The theoretical results have been verified by measurements. Based on the theoretical results, a simple circuit configuration has been developed which reduces the time constant of the loop filter for acquisition and so prevents false lock.