Clock tree synthesis with methodology of re-use in 3D IC

Abstract

IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimension integrated circuit (3D IC). In order to achieve manufacturing reuse, in this paper, we propose a new methodology to design a global clock tree in 3D IC. The objective is to extend an existing clock tree in 2D IC to 3D IC taking into consideration the wirelength, clock skew and the number of TSVs. Compared with NNG-based method, our proposed method reduces the wirelength of the new die and skew of the global 3D clock tree, on an average, 47.16% and 5.85%, respectively.