{"title":"Voltage differencing transconductance amplifier based fractional order multiple input single output universal filter","authors":"Parveen Rani, Rajeshwari Pandey","doi":"10.1016/j.ssel.2020.01.006","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper a Voltage Differencing Transconductance Amplifier (VDTA) based Voltage Mode (VM) Multi Input Single Output (MISO) Fractional Order filter (FOF) providing all five filter responses is presented. The proposed FOF is designed using single VDTA and two fractional Capacitors (FC). The FC is implemented using RC ladder network; component values of which are computed using Carlson rational approximation. For illustration, FC of 0.5 order has been implemented using first, second and third iterations of Carlson approximation, which results in different integer order approximation functions. The ladder component values for all iterations are computed using MATLAB. The effect of different iterations on FOF behavior is also studied. The proposed FOF is verified through Cadence Virtuoso simulations using 0.18 µm CMOS technology.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"1 2","pages":"Pages 110-118"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.01.006","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid State Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2589208820300065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper a Voltage Differencing Transconductance Amplifier (VDTA) based Voltage Mode (VM) Multi Input Single Output (MISO) Fractional Order filter (FOF) providing all five filter responses is presented. The proposed FOF is designed using single VDTA and two fractional Capacitors (FC). The FC is implemented using RC ladder network; component values of which are computed using Carlson rational approximation. For illustration, FC of 0.5 order has been implemented using first, second and third iterations of Carlson approximation, which results in different integer order approximation functions. The ladder component values for all iterations are computed using MATLAB. The effect of different iterations on FOF behavior is also studied. The proposed FOF is verified through Cadence Virtuoso simulations using 0.18 µm CMOS technology.