A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques

Abstract

In view of the remarkable progress in MPU performance, improvement in the data rate of L2 cache SRAMs is desirable to maximize system performance. As a solution, Double-Data-Rate (DDR) SRAMs, which can realize an I/O frequency of up to twice that of conventional Single-Data-Rate (SDR) SRAMs, have been reported. Increase in operation-current due to higher operation frequency causes severe power-line noise and heating. Therefore, reduction of operation-current is an important issue in designing high-speed SRAMs. In order to realize both high-frequency operation and power reduction, we propose new sense circuitry and a bit-line load scheme.