Power integrity investigation of BGA footprints by means of the segmentation method

Abstract

The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on PCB's. In fact, providing the required power to the different IC's at the specified noise-free voltage levels allows a correct functioning of the overall PCB systems. More over, the ongoing trend of replacing active devices with peripherally located I/O and PWR/GND pins with areally located I/O and PWR/GND pins (BGA packaged) increases the complexity of the models, when power delivery issues need to be studied in a larger contest, such as the overall PCB's. The employment of the powerful, but simple, concept of the segmentation method allows investigation of the power delivery network of the PCB systems in two fundamental stages. During the first stage, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool. During the second stage the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method, with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach