Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility

T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, S. Takagi
{"title":"Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility","authors":"T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, S. Takagi","doi":"10.1109/IEDM.2002.1175772","DOIUrl":null,"url":null,"abstract":"Physical mechanisms responsible for the reduction in both electron and hole mobility in thin strained-Si structures of strained-SOI CMOS devices are examined in detail. The slight decrease in electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect in strained-Si layers. Also, diffusion of Ge atoms into SiO/sub 2//strained Si interface is found to cause the generation of interface states near valence band edge, leading to the reduction in hole mobility in lower E/sub eff/ region through Coulomb scattering. Based on considerations of these factors affecting mobility, the strained-Si thickness and the Ge content are designed to realize high-speed strained-SOI CMOS under the 65 nm technology and beyond.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"1 1","pages":"31-34"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21

Abstract

Physical mechanisms responsible for the reduction in both electron and hole mobility in thin strained-Si structures of strained-SOI CMOS devices are examined in detail. The slight decrease in electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect in strained-Si layers. Also, diffusion of Ge atoms into SiO/sub 2//strained Si interface is found to cause the generation of interface states near valence band edge, leading to the reduction in hole mobility in lower E/sub eff/ region through Coulomb scattering. Based on considerations of these factors affecting mobility, the strained-Si thickness and the Ge content are designed to realize high-speed strained-SOI CMOS under the 65 nm technology and beyond.
具有更高载流子迁移率的缩放薄膜应变soi CMOS器件的设计
详细研究了应变soi CMOS器件中应变si薄结构中电子和空穴迁移率降低的物理机制。电子迁移率随应变si层变薄而略有下降,这是由于应变si层中的量子力学约束效应。同时,发现Ge原子向SiO/sub 2/应变Si界面的扩散导致价带边缘附近界面态的产生,通过库仑散射导致低E/sub /区域的空穴迁移率降低。基于这些影响迁移率的因素,设计了应变si厚度和Ge含量,以实现65 nm及以上工艺下的高速应变soi CMOS。
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4.50
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