Development of multi-stack dielectric wafer bonding

Abstract

We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.