Die-to-Wafer 3D Interconnections Operating at Sub-Kelvin Temperatures for Quantum Computation

Abstract

To reach quantum supremacy, large scale integration of quantum bits through three dimensional (3D) architectures functional at sub-Kelvin temperatures is required. Electrical signals are transferred by 3D interconnects which need to be carefully designed in term of materials and dimensions to optimize the whole system performance. To that end, 20 μm pitch daisy chains with more than 20000 SnAg microbump-based interconnects and more than 1000 direct Cu bond ones have been fabricated with die-to-wafer processes developed on 300 mm Si wafers. Daisy chain resistances have been measured in a liquid nitrogen deware and in a He3 cryostat at the following thermal steps: 300 K, 77 K, 4 K and 400 mK, allowing to extract unitary link resistances to establish preliminary process design kits at these low temperatures. The mechanical and electrical robustness of these interconnects has been validated through the repeatability of the resistance measurements over several thermal cycles.